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drmosproductfamily drmos5x5 TDA21231 datasheet rev.2.0 final powermanagementandmultimarket
TDA21231 data sheet 1 1 applications ? desktop and server vr buck-converter ? single phase and multiphase pol ? cpu/gpu regulation in notebook, desktop graphics cards, ddr memory, graphic memory ? high power density voltage regulator modules (vrm) 2 features ? for synchronous buck converter step down voltage applications ? maximum average current of 55 a ? input voltage range +4.5 v to + 16 v ? power mosfets rated 25 v ? fast switching technology for improved performance at high switching frequencies (> 500 khz) ? remote driver disable function ? includes bootstrap diode ? undervoltage lockout ? shoot through protection ? +5 v high side and l ow side mosfets driving voltage ? compatible to standard +3.3 v pwm controller integrated circuits ? tri-state pwm input functionality ? small package: pg -iqfn- 31 - 2 (5 x 5 x 0.8 mm3) ? rohs compliant ? thermal warning table 1 product identification part number temp range package marking TDA21231 -25 to 125 ? c pg -iqfn- 31 -2 (5 x 5 x 0.8 mm3) da21231 figure 1 picture of the product
TDA21231 data sheet 2 3 description 3.1 pinout figure 2 pinout, numbering and name of pins (transparent top view)
TDA21231 data sheet 3 table 2 i/o signals pin no. name pin type buffer type function 1 pwm i +3.3 v logic pwm drive logic input the tri-state pwm input is compatible with 3.3 v. 5 boot i analog bootstrap voltage pin connect to boot capacitor 6 gh o analog high-side gate test point for high side mosfet gate signal 7 phase i analog switch node (reference for boot voltage) internally connected to sw pin, connect to boot capacitor 16 C 23 sw o analog switch node output high current output switching node 27 gl o analog low -side gate test point for low side mosfet gate signal 30 phflt# o +3.3 v logic thermal warning connect through a resistor to 3.3v. when the thermal protection threshold is tripped, the phflt# pin is being pulled low. leave open if not used. 31 en i +3.3 v logic enable signal (active high) connect to gnd to disable the ic. table 3 power supply pin no. name pin type function 8 to 11, vin pad vin power input voltage supply of the drain of the high-side mosfet 29 pvcc power fet gate supply voltage high- and low-side gate drive supply 3 vcc power logic supply voltage bias voltage for the internal logic table 4 ground pins pin no. name pin type function 4 agnd gnd control signal ground should be connected to pgnd externally 12 C 15, 28, pgnd pads pgnd gnd power ground all these pins must be connected to the power gnd plane through multiple low inductance vias. table 5 not connected pin no. name pin type function 2 nc C no internal connection leave pin floating or tie to noise- free voltage of 0 (gnd) 7 v . 24, 25, 26 nc C no internal connection options: leave floating, tie to gnd or sw
TDA21231 data sheet 4 3.2 general description the infineon TDA21231 is a multichip module that incorporates infineons premier mosf et technology for a single high-side and a single low-side mosfet coupled with a robust, high performan ce, high switching freq ue ncy gate driver in a single pg -iqfn- 31 - 2 package. the optimized gate timing allows for significant light load efficiency improvements over discrete solutions. when combined with infineons family of digital multi-phase controllers, the TDA21231 forms a complete cor e- voltage regulator solution for advanced micro and graphics processors as well as point- of -load applications. figure 3 simplified block diagram
TDA21231 data sheet 5 4 electrical specification 4.1 absolute maximum ratings note: t a = 25c stresses above those listed in table 6 absolute maximum ratings may cause permanent damage to the device. these are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational s ections of this specification. exposure over values of the recommended ratings (table 8) for extended periods may adversel y affect the operation and reliability of the device. table 6 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. maximum average load current i out C C 55 a input voltage v in (dc) - 0.30 C 21 v logic supply voltage v vcc (dc) - 0.30 C 8 high- and l ow -side driver voltage v pvcc (dc) - 0.30 C 8 switch node voltage v sw (dc) -1 C 25 v sw (ac) -8 1 C C phase node voltage v phase (dc) -1 C 25 v phase (ac) -8 1 C C mosfet voltage spike v in -v phase (ac) C C 32 2 2 ns above 25 v v phase -v pgnd (ac) C C 32 2 boot voltage v boot (dc) - 0.3 C 25 v boot (ac) C C 30 1 v boot -phase (dc) - 0.3 C 8 en voltage v en - 0.3 C 4 maximum value valid for operation up to 1h accumulated over lifetime in temperature range of - 25?c tj 125?c. else the maximum value is 3.6v pwm voltage v pwm - 0.3 C 4 phflt# v phflt# - 0.3 C 4 junction temperature t jmax - 40 C 150 ? c storage temperature t stg - 55 C 150 note: all rated voltages are relative to voltages on the agnd and pgnd pins unless otherwise specified. 1 ac is limited to 10 ns 2 ac is limited to 2 ns
TDA21231 data sheet 6 4.2 thermal characteristics table 7 thermal characteristics parameter symbol values unit note / test condition min. typ. max. thermal resistance to case (soldering point) jc C C 2 k/w C thermal resistance to top of package j ctop C C 30 C thermal resistance to ambient (p loss = 4.5 w,t a = 70 c, 8 layer server board with 2 oz copper per layer ) ja C 1 1.5 C still air C 8.9 C 200 lfm airflow C 8.8 C 300 lfm airflow 4.3 recommended operating conditions and electrical characteristics note: v drv = v cin = 5 v, t a = 25c table 8 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. input voltage v in 5 C 16 3 v for telecom applications see note 3 mosfet driver voltage v pvcc 4.5 5 7 logic supply voltage v vcc 4.5 5 7 frequency of the pwm f sw C C 1.2 mhz junction temperature t jop - 25 C 125 c 3 in telecom applications the recommended maximum voltage fo r v in is 13.2v unless a boot resistor is used (see figure 6) to limit the voltage spike v phase -v pgnd (ac) to 26v.
TDA21231 data sheet 7 table 9 voltage supply and biasing current parameter symbol values unit note / test condition min. typ. max. uvlo boot rising v uvloboot_r C 4.0 C v v boot -v sw rising uvlo boot falling v uvloboot_f C 3.8 C v boot -v sw fa lling uvlo rising v uvlo_r C C 4.2 v vcc rising uvlo falling v uvlo_f 3.7 C C vcc falling driver current i pvcc_300khz C 15 C ma en = 3.3 v, f sw = 300 khz i pvcc_1mhz C 50 C en = 3.3 v, f sw = 1 mhz i pvcc_pwml C 71 0 C a en = 3.3 v, pwm = 0v i pvcc_pwmh C 2 10 C en = 0v, pwm=3.3v, ic current (control) i vcc_pwml C 1 C ma en = 3.3 v, pwm = 0 v i vcc_o C 630 C a en = 3.3 v, pwm = open ic quiescent i cc + i pvcc C 84 0 C en = 0v, pwm = open pre-bias at sw v sw_0 C 160 180 mv vcc and pvcc present table 10 logic inputs and threshold parameter symbol values unit note / test condition min. typ. max. en input low v en _l C C 0.8 v v en falling input high v en _h 2.0 C C v en rising sink current i en C 10 C a v en = 1 v pwm input low v pwm_l C C 0. 6 v v pwm falling input high v pwm_h 2. 6 C C v pwm rising input resistance r in -pwm C 2 C k ? v pwm = 1 v open voltage v pwm_o C 1.6 C v v pwm_o tri-state shutdown window 4 v pwm_s 1. 2 C 2. 0 phflt# warning temperature 5 t phflt #_t C 140 C c thermal warning accuracy 5 dt phflt #_t - 10 C 10 k hysteresis 5 t phflt #_h C 10 C on resistance r phflt#_pd C 37.5 80 i load = 8ma leakage current i phflt#_lk C 0.1 5 a 4 maximum voltage range for tri-state 5 the thresholds for temperature warning are verified by design and not subject to production test.
TDA21231 data sheet 8 table 11 timing characteristics parameter symbol values unit note / test condition min. typ. max. pwm tri-state to sw rising delay t_pts C 15 C ns pwm tri- st ate to sw falling delay t_pts 2 C 15 C sw shutdown hold-off time from pwm low t_tsshd C 50 C sw shutdown hold-off time from pwm high t_tssh C 50 C pwm to sw turn-off propagation delay t_pdlu C 20 C pwm to sw turn- on propagation delay t_pdll C 10 C dr_en turn-off propagation delay falling t_pdl_dr_en C 20 C dr_en turn-on propagation delay rising t_pdh_dr_en C 20 C uvlo-boot-on time t_uvlobooton C 200 C pulse pattern issued to gl in uvlo-boot uvlo-boot-off time t_uvlobootoff C 200 C pwm minimum pulse width ton_min_pwm C 25 C when pwm change is recognized, the output remains in the new state for these minimum times. pwm minimum off time toff_min_pwm C 30 C 5 theory of operation the TDA21231 incorporates a high performance gate driver, one high-side power mosfet and one low-side power mosfet in a single pg -iqfn- 31 - 2 package. the advantages of this arrangement are found in the areas of increased performance, increased efficiency and lower overall package an d layout inductance.this module is ideal for use in synchronous buck regulators. the power mosfets are optimized for 5 v gate drive enabling excellent high l oad and light load efficiency. the gate driver is a robust high-performance driver rated at the switching node for dc vol tages ranging from -1 v to +2 1 v. the power density for transmitted power of this approach is approximately 90 w within a 25 mm 2 area. 5.1 driver characteristics the gate driver of the TDA21231 has 2 voltage inputs, vcc and pvcc . vc c is the 5 v logic supply for the driver. pvcc sets the driving voltage for the high side and l ow side mosfets. the reference for the gate driver control circuit (vcc) is agnd. to decouple the sensitive control circ uitry (logic supply) from a noisy environment a ceramic capacitor must be placed between vcc and agnd close to the pi ns. pvcc needs also to be decoupled using a ceramic capacitor (mlcc) between pvcc and pgnd in close prox imity to the pins. pgnd serves as reference for the power circuitry including the driver output stage.
TDA21231 data sheet 9 referring to the block diagram page 4 , vc c is internally connected to the uvlo circuit. it will force shut-down for insufficient vcc voltage. pvcc supplies the floating high-side drive C consisting of an active boot circuit - and the low side drive circuit. during undervoltage both gh and gl are driven low actively ; further passive pull- down (10 k ? ) is placed across gate-source of both fets. an additional uvlo circuitry, sensing the boot voltage level, is implemented to enable a recharge of the boot capacitor when its voltage is too low for a complete turn-on of the hs-mosfet. 5.2 inputs to the internal control circuits the pwm is the control input to the ic from an external pwm controller and is compatible with 3.3 v. the pwm input has tri-state functionality. when the voltage remains in the spe cified pwm-shutdown-window for at least the pwm-shutdown-holdoff time t_tsshd, the operation will be suspended b y keeping both mosfet gate outputs low. once left open, the pin is held internally at a level of v pwm_o = 1.6 v level. table 12 pwm pin functionality pwm logic level driver output low gl= high, gh = low high gl = low, gh = high open (left floating, or high impedance) gl = low, gh = low the pwm threshold voltages v pmw_o , v pwm_h , v pwm_l do not vary over the wide range of vcin supply voltages (4.5 v to 8 v). the en is an active high signal. when en is being pulled low, the power stage will be disabled. figure 4 enable (en) signal logic levels v cc h l v en_l v en_h en logic level shutdown enable
TDA21231 data sheet 10 table 13 en pin functionality en logic level driver output low shutdown : gl = gh = low high enable : gl = active, gh = active open (left floating, or high impedance) shutdown : gl = gh = low 5.3 thermal protection the phflt# pin is a digital monitoring output for the thermal warning. it does not affect the operation of the driver nor does it shut down the device. when the driver junction temperature exceeds the thermal warning threshold of 140 c (typ) the open drain output phflt# will be pulled low. externally phflt# has to be connected to a su pply (e.g. +3.3 v) by a resistor in the range of 10 k ?? when the temperature of the driver junction decreases below the level of therm al warning threshold minus hysteresis ( 10 k typ.), the pin phflt# is released. v phflt # is being pulled up by the external resistance. if the thermal warning feature is not used the pin can be left floating. figure 5 thermal warning 5.4 shoot through protection the TDA21231 driver includes gate drive functionality to protect against shoot th rough. in order to protect the power stage from overlap, both high-side and lo w-side mosfets being on at the same time, the adaptive control circuitry monitors specific voltages. when the pwm signal transiti ons to low, the high-side mosfet will begin to turn off after the propagation delay time t_pdlu. when v gs of the high-side mosfet is discharged below 1 v (a threshold below which the high-side mosfet is off), a secondary delay t_pdhl is initiated. after that delay the l ow -side mosfet turns on r egardless of the state of the sw pin. it ensures that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropria tely during each switching cycle. see figure 8 for more detail. h l t phflt#_ t - t phflt#_h t phflt#_t t j phflt# output logic level hysteresis rising temperature falling temperature
TDA21231 data sheet 11 5.5 uvlo C boot protection after long tristate conditions the voltage of the boot capacitor may be too small to completely enhance the hs- mosfet when pwm enables gh directly after. therefore, a monitoring circuit is being implemented to detect a lower threshold at which gh can safely be turned on. if the voltage across the boot c apacitor has been dropping to this threshold a boot refresh circuit engages until an upper threshold has been reached. the recharge is being done by intervals of repetitively pulling gl hi gh for t_uvlobooton followed by t_uvlobootoff driving gl low to reset the output current to zero. when the voltage acros s the boot capacitor has reached an upper threshold the recharge cycles stop. the pwm input always takes priority over the boot refresh circuit when it is logic h or logic l. 6 application 6.1 implementation figure 6 pin interconnection outline (example, transparent top view) note: 1. pin phase is internally connected to sw node 2. it is recommended to place a rc filter between vcc and pv cc as shown. 3. pins 24, 25 and 26 are not internally connected. one can leave them open or connect to gnd or to sw . 4. r boot is only required for telecom applications with v in > 13.2v (see table 8). if necessary, its value should be selected to limit the voltage spike v phase -v pgnd (ac) to 26 v.
TDA21231 data sheet 12 6.2 typical application figure 7 six-phase voltage regulator - typical application (simplified schematic)
TDA21231 data sheet 13 7 gate driver timing diagram figure 8 adaptive gate driver timing diagram pwm gl gh 1 v tri-state v pwm_l t_pdhl t_ tsshd t_pdll t_pdhu t_ pdlu v pwm_l t_ tssh t_pts2 t_pts sw note : sw during entering/exiting tri-state behaves dependend on inductor current. 1 v 1 v (threshold for gl enable) v pwm_h v pwm _h v pwm_h
TDA21231 data sheet 14 figure 9 en timing diagram en sw t_pdl(en) v en _l t_pdh(en) v en _h active active deactivated
TDA21231 data sheet 15 8 mechanical drawing pg - iqfn - 31 - 2 figure 10 mechanical dimensions (in mm)
TDA21231 data sheet 16 figure 11 recommended landing pattern and stencil dimensions (in mm)
TDA21231 data sheet 17 9 board layout recommendations the pcb (printed circuit board) layout design follows the listed industry standards: - recommended vias: 10 mil 6 hole with 20 mil via pad diameter, 12 mil hole with 24 mil via pad diameter - minimum (typical) via to via center distance: 25 mil (30 35 mil) - minimum feature width: 5 mil - minimum (typical) clearance: 5 mil (15 20 mil) commonly, 10 mil via drill diameters are used for pcbs up to 150 mil thicknesses (usually 22 layers). for thicker boards, 12 mil vias are recommended. to reduce voltage spikes caused by p arasitic circuit inductance, all primary decoupling capacitors for vin, pvcc, boot and vcc should be of mlcc type, x6s or x7r rated and located at the same board side as the powerstage close to their respective pins. this is espec ially important for the vin to pgnd mlccs. electrical and thermal connection of the powerstage to the pcb is crucial for achieving high efficiency. therefore, vias in vin and pgnd pads are required in the pad areas to connect most effectively to other power and pgnd layers. bigger value mlcc input capacitors should be placed at the bottom side of the pcb close to the vias of the powerstages vin and pgnd pads. to reduce the stray inductance in the current commutation loop it is strongly recommended to have the 2 nd layers from the top and the bottom of the board to be monolithic ground planes. all logic and signal connections between powerstage and controller sho uld be embedded between two ground layers. the routing of the current sense lines back to the c ontroller has to be done differentially, for example with 5 mil spacing and 10 C 15 mil distances to other potentials. if the pcb features more than 10 layers, the passive components associated with the current sense lines should be located only at the top side of the board. all resistors and capacitors near the powerstage should be in 0402 case size. for minimizing distribution loss to the load and maintaining signal integrity, h ave multiple layers/planes in parallel and ensure that the copper cross section for pgnd is at least as big as it is for vout. figure 12 generic board design 6 unit conversion: 1 mil = 25.4 m
19 drmos5x5 TDA21231 rev.2.0,2015-04-23 revisionhistory TDA21231 revision:2015-04-23,rev.2.0 previous revision revision date subjects (major changes since last revision) 1.0 2015-03-24 release of preliminary version 2.0 2015-04-23 release of final version welistentoyourcomments anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com publishedby infineontechnologiesag 81726mnchen,germany ?2015infineontechnologiesag allrightsreserved. legaldisclaimer theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics.with respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication ofthedevice,infineontechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithout limitation,warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. information forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestinfineon technologiesoffice( www.infineon.com ). warnings duetotechnicalrequirements,componentsmaycontaindangeroussubstances.forinformationonthetypesinquestion, pleasecontactthenearestinfineontechnologiesoffice. theinfineontechnologiescomponentdescribedinthisdatasheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofinfineontechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered.

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